Chapter 14. Computer Architecture Excerpted from the 1994 Research Summary
(Copyright 1994, UC Regents)

Contact person: Carol Block, ILP Coordinator
(ilp@hera.eecs.berkeley.edu)
510.643-6691, 643-6694 fax


The computer architecture and systems area pursues a vigorous program
of applied research at the intersection of computer systems design,
performance evaluation, computer-aided design techniques,
integrated circuit technology, and parallel computing.

Major efforts are under way in the design and analysis of parallel
computer and storage systems. As CPU speeds outstrip memory and I/O
speeds, memory hierarchy performance becomes the limiting factor in
most modern general purpose computers. Professors Randy Katz, David
Patterson, and Alan Smith are supervising a variety of projects that
deal with the management of the memory hierarchy, spanning from
processor caches to tertiary storage systems.

The RAID Project, under the direction of Professor Katz, in conjunction
with Professor John Ousterhout and Professor Patterson, is reaching its
culmination with the implementation of a prototype disk array file
server with a capacity of 40 GBytes and a sustained bandwidth of 80
MBytes/second. The server is being interfaced to a 1 Gb/s local area
network. A new initiative, which is part of the Sequoia 2000 Project,
seeks to construct a geographically distributed storage system spanning
disk arrays and automated libraries of optical disks and tapes. The
project will extend the interleaved storage techniques so successfully
applied to disks to tertiary storage devices. A key element of the
research will be to develop techniques for managing latency in the I/O
and network paths.

The research facilities in the division include a 128-processor
Connection Machine CM-5, which supports a number of faculty
investigations in parallel processing, led by Professors David Culler,
Katherine Yelick, Thomas Anderson, James Demmel, and Abhiram Ranade.
Their interests focus on developing parallel computer systems,
including algorithms and languages for parallel processors,
communication in parallel processing systems, and VLSI implementations
of parallel processors. In addition, a highly parallel machine tailored
to connectionist neural network applications is being developed by
Professors John Wawrzynek and Jerome Feldman in conjunction with the
International Computer Science Institute.