14.arch/DEC.kyi .ls 2 .na .LP VHDL Mixed-Level Parallel Simulation Theodore Kyi (Professor D. E. Culler) (NSF) CCR-90-58432 (PYI) and Semiconductor Research Corporation The development of leading-edge VLSI systems is becoming increasingly simulation-intensive as designs become more complex, more costly to fabricate, and more sensitive to the "time to market." The designer literally needs to boot the operating system on the simulated processor at every level, from a high-level behavioral description down to the final netlist. Modern hardware description languages, such as VHDL, support a consistent process of design refinement; however, as the level of description is refined, we are faced with a growth of 3 orders-of-magnitude or more in the number of processes. Current VHDL simulators spend as much as 98% of their time in scheduling and data conversion for gate-level designs. The objective of this project is to dramatically increase the simulation throughput of very large, detailed hardware descriptions using two techniques: sophisticated compilation of the description and application of parallelism to the simulation. These two techniques are in concert, since the compilation techniques also increase the granularity at which work is scheduled across processors. The compilation process involves first translating into a process-signal flow graph and then using the structure and event spacing of the flow graph to partition it into efficiently schedulable regions. The basic approach partitions the graph into collections of fan-in and fan-out trees. Within a tree, localized scheduling is compiled into the code produced for the collection of processes comprising the tree. Dynamic global scheduling is performed across tree regions. We are implementing these compilation strategies and our hierarchical scheduling techniques using an existing VHDL front end. The performance of the modified simulator is being measured on large gate-level designs.