14.arch/AJS.tse
.ls 2
.na
.LP
Performance Evaluation of Cache Pre-Fetch Algorithms

John Tse

(Professor A. J. Smith)

MICRO,
Mitsubishi Electric,
(NSF) MIP-91-16578,
Philips Laboratories/Signetics, and
Sun Microsystems

Cache pre-fetching can substantially reduce miss ratios for caches, but
a number of factors, including bus traffic, access contention, and
timing delays, have severely limited the utility of pre-fetching.

We are using a memory system simulator that accurately reproduces
timing effects, and we are driving it with a variety of program address
traces. These analyses will help us to study the following issues: 1)
performance comparison of different cache pre-fetching algorithms,
assuming realistic access time and access interference to the cache;
2) how much miss ratio reduction and memory traffic increase can be
expected as a function of line size, cache size, cache type, and
pre-fetching algorithms;  3) what hardware features are needed (e.g.,
dual ported tags, dual ported data arrays, split transaction bus, write
buffers, write-back buffers, etc.) in order to allow the reduction in
miss ratio obtained from pre-fetching to be reflected in improved
performance.