14.arch/JW.callahan
.ls 2
.na
.LP
Network Design for the Connectionist Network Supercomputer

Tim Callahan 

(Professor J. Wawrzynek)

NSF Graduate Fellowship, 
(NSF) CDA-87-22788, and
(ONR) URI-N00014-92-J-1672 

This project focuses on designing the communications network for the
Connectionist Network Supercomputer (CNS-1). The CNS-1 is a massively parallel computer based on a
processor that integrates an MIPS CPU core, a fixed-point vector unit,
and a network interface on a single chip. 

This work involves two parts: design and implementation of the CNS-1
communications network, and definition and implementation of the
network interface to the CPU core and vector unit.

We have developed a network simulator that runs on the Thinking
Machines' CM-5 computer. The simulator is implemented using the C++
language; the C++ objects are spread across the CM-5 nodes and
communicate using logical links provided by the simulator framework.
The simulator has been designed to be flexible; the underlying
framework can be used to perform any distributed synchronous
simulation. In this project, simulations have been performed to
compare candidate network protocol and buffering strategies for the
CNS-1 machine. Through simulations we are comparing design choices to
find the best combination of high performance and design simplicity.
Important design issues include the width and speed of the physical
links, the routing algorithm, the flow control mechanism, and the
sizes of the buffers in the network.

We have defined the network interface by adding coprocessor
instructions and state to the MIPS instruction set architecture. This
interface reflects our CNS-1 design goal of efficient communication of
small messages. The network interface is based on the Active Message
mechanism of Thorsten von Eicken and exhibit characteristics suggested
by other researchers:  sending and receiving messages directly into CPU registers;
low CPU overhead for sending and receiving;
and multiple sets of registers for composing messages. Another goal of this design is to define the instruction set
extensions so that they are straightforward to use by the
software, allow high-speed implementation, and mesh cleanly
with the existing MIPS instruction set. Specification of the network
interface has been completed, and work on its VLSI implementation has
begun.