Delay Constraints and Admission Control in ATM networks



                       Petia Todorova
   Research Center for Open Communication Systems (FOKUS)
                     Hardenbergplatz 2
                      D-1000 Berlin 12
                         FR Germany
                   Phone: 49-30-25499-251
                  Telefax:49-30-25499-202



                        Dinesh Verma
                Computer Science Department,
                      571 Evans Hall,
                 University of California,
                    Berkeley, CA-94720,
                   Phone: (415) 642-8919
                   Telefax:(415) 642-5775




                          Abstract



     This article first reviews the architecture of a  typi-
cal  ATM  switch  and considers the problem of handling both
continuous bit oriented and bursty traffic with low loss and
delay requirements. We examine a buffer architecture that is
capable of handling both delay sensitive and loss  sensitive
traffic, and present a scheme to allocate network resources,
i.e. bandwidth and buffer space, to individual  circuits  to
ensure acceptable delay and loss performance.