Resource Allocation and Delay Constraints in ATM networks



                       Petia Todorova
   Research Center for Open Communication Systems (FOKUS)
                     Hardenbergplatz 2
                      D-1000 Berlin 12
                         FR Germany
                   Phone: 49-30-25499-251
                  Telefax:49-30-25499-202



                        Dinesh Verma
                Computer Science Department,
                      571 Evans Hall,
                 University of California,
                    Berkeley, CA-94720,
                   Phone: (415) 642-8919
                   Telefax:(415) 642-5775




                          Abstract

     This article first reviews the architecture of a  typi-
cal  ATM  switch  and considers the problem of handling both
continuous bit oriented and bursty traffic with low loss and
delay  requirements.  We examine six different approaches to
handling mixed traffic in an ATM switch, and  compare  their
performance  by  means  of simulation. A switch architecture
which distinguishes  between  three  traffic  types  with  a
shared  buffer turns out to have the best performance, where
by performance we mean the ability of the switch to  provide
the  quality  of  service  (loss and delay ) desired by each
application at minimum expense.